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DFT Engineer - ASIC/IC/SoC

We are seeking bright candidates with a strong academic record and 5-10 years’ experience in Design for Test (DFT) within digital and mixed-signal ASIC/SoC development. You will be familiar with the challenges of architecting, specifying, and implementing DFT within complex ASIC/SoC designs, most of which include power management, memories, and Analog IP elements such as PLLs, ADC/DAC, and SerDes PHY’s. You will also have experience with automatic and manual test-pattern generation flows, fault coverage analysis, and MBIST implementation. Key tasks / responsibilities : * Take full-flow ownership of all DFT, MBIST, and test-pattern generation for complex digital and mixed-signal ASIC designs on an as-needed basis to meet customer project requirements * Provide Test-related consultancy to customers both in the pre-sales and implementation stages. * Setup, run, and maintain EDA tool flows relating to DFT, MBIST, and test pattern generation * Work closely alongside the Front-end and Back-end teams to implement and verify DFT at all stages in the development flow * Take responsibility for setting and meeting customer’s fault-coverage expectations and requirements * Be the primary interface for any back-end service companies that may be sub-contracted to develop hardware or test programs * Generate test specification documentation, as required, for delivery to sub-contractors providing test services * Keep up to date with all aspects of ASIC Test methodology and best-practice to ensure that expertise and services are always current and appropriate for each customer project Key skills / Background : * 1st or 2.1 Electronics, Physics or relevant subject * 5-10 years’ experience in industry with a strong track record in DFT gained across several successful ASIC projects, and ideally at process nodes down to and including 16FF Specific skills in DFT implementation: * Specification at the architecture level * Implementation using tool-based and hand-crafted methods * Integration of IP including CPU’s, Analog Macros, and IO PHYs * MBIST and memory repair integration * Coverage analysis and improvement to meet targets * ATPG, as well as manual and semi-automatic TPG, including simulation-based methods * Implementation of at-speed test methodologies * DFT for power-managed designs * Generation of STA and scenario/mode constraints * Knowledge of the full Synopsys or Mentor Tessent DFT tool kit(s) would be advantageous, including the use of LEQ, simulators, and STA tools for verification * Working knowledge of the complete SoC design flow and associated tools and methodologies to deliver working silicon * Experience of RTL and gate-level simulation as applied to DFT verification * VHDL/Verilog coding skills * Experience working with test service providers is desirable, including test hardware specification, test program specification, test program bring-up and debug, yield analysis and enhancement